Generator of a time interval as a multiple of a base period

ABSTRACT

A standard time interval having a well-defined duration for use as a time measurement reference is delimited by two fronts separated by N periods of an oscillation having a preferably rectangular waveform and produced by a frequency standard oscillator. The generator comprises a trigger circuit which transmits clock pulses and synchronizes them with the fronts derived from the oscillator, a preset counting register operated by the clock pulses, two detectors for selecting the active clock-pulse fronts and each comprising a delay line, two amplifying circuits for collecting the active fronts and converting them into utilizable signals.

mte tates ate 3 1 1 1111 3,739,199 Negrou June 12, 1973 [54] GENERATOROF A TIME INTERVAL AS A 3,509,473 4/1970 Porta 328/129 X L I L OF A BASEPERIOD 3,564,426 2/1971 Anderson et al. 328/48 3,657,658 4/1972 Kubo328/48 X Inventor: Jacques Negrou, Gesta, France Commissariat A LEnergieAtomique, Paris, France Dec. 16, 1971 Assignee:

Filed:

Appl. No.:

References Cited UNITED STATES PATENTS 11/1966 Poole 328/48 8/1950Grosdoff 328/48 12/1960 Sterk 328/129 X 3/1966 Madsen et al 328/48 X2/1968 Mester 328/48 Primary ExaminerStanley D. Miller, Jr.Attorney-William B. Kerkam, Jr.

[57] ABSTRACT A standard time interval having a well-defined durationfor use as a time measurement reference is delimited by two frontsseparated by N periods of an oscillation having a preferably rectangularwaveform and produced by a frequency standard oscillator.

The generator comprises a trigger circuit which transmits clock pulsesand synchronizes them with the fronts derived from the oscillator, apreset counting register operated by the clock pulses, two detectors forselecting the active clock-pulse fronts and each comprising a delayline, two amplifying circuits for collecting the active fronts andconverting them into utilizable signals.

8 Claims, 8 Drawing Figures PD COUNTDOWN REGISTER AMPLIFIERS OOINCIDENCEcmculr l Patented June 12, 1973 4 Sheets-Shut 2 JREQUENCY OSCILLATORMONOVIBRATOR 93%? NC I F42 DIFFERENTIATOR 70 AL M monv FIG-4 74/1DIRECTBIAS CURRENT GENERATOR MEMORY CELLS DIODE SNAP-OFF Patented June12, 1973 4 Shack-Shoo 3 nmol mOhumhwo HER "Kuhn-0mm ZBOOFZDOO PatentedJune 12, 1973 3,739,199

4 Sheets-Sheet 4 GENERATOR OF A TIME INTERVAL AS A MULTIPLE OF A BASEPERIOD This invention relates to the controlled production of a standardtime interval, that is to say of a time interval having a duration whichis defined and known with a high degree of accuracy in order txat it maybe used as a time measurement reference.

It is already a known practice to make use of the socalled frequencystandards such as oscillator devices which deliver a periodic signalhaving a particularly stable and well defined period T and to apply thepotentialities offered by these devices to the production of timestandards (atomic clock, for example). However, it is not possible toproduce a standard time interval and one interval alone by means ofthese methods or by means of the devices for carrying them out and theduration of this interval cannot be varied at will.

This invention is directed to a standard time generator which employs asin the prior art a periodic oscillation having preferably asubstantially rectangular waveform and a known period T, saidoscillation being produced by a frequency standard oscillator. A numberN of periods is counted from a predetermined instant which defines thebeginning of the standard time interval and the instant which terminatesthe N" period defines the end of the standard time interval.

If the generator collects two frequency standard clock-pulse frontswhich are spaced at a distance of N periods and employs these latter inorder to initiate a certain number of operations in complex circuits,the standard obtained as an end result is finally delimited by electricsignals produced by said circuits from the clock-pulse fronts.

A number of difficulties are encountered in the practical definition ofthe standard time interval and these are mainly as follows:

the two clock-pulse fronts which will serve to define the beginning andthe end of the standard interval must be isolated without disturbingthis latter;

the two channels for transferring said clock-pulse fronts into thegenerator must be identical from the electrical point of view and mustespecially have the same transit time;

each clock-pulse front which is employed must be translated in a highlyreproducible manner up to the output of the circuits of the generator.

A preferred alternative embodiment of this invention is concerned with astandard time interval generator which makes it possible to overcome thedisadvantages referred-to above and in which the clock-pulse frontsthemselves define directly and without any intermediate generatorcircuit the limits of the standard time interval which it is desired toproduce since the clock is coupled directly to the output circuits ofthe generator.

This alternative embodiment does not directly employ the pulse frontscollected at the output of detectors which serve to detect the first andN" pulse fronts but employs them as gate-control signals in order toobtain synchronization with the clock. In consequence, the n" and (Nn.)" pulse fronts are transmitted to output amplification and shapingcircuits.

The generator for producing a standard time interval 1' NT delimited bytwo fronts separated by N periods of a periodic and preferablysubstantially rectangular oscillation having a period T and generated bya frequency standard oscillator, is characterized in that it comprisesin combination:

a circuit for triggering and synchronizing with the fronts derived fromthe frequency standard oscillator, only those pulses of said oscillatorwhich come after an order given by said trigger circuit and arereferred-to as clock pulses being transmitted by means of said circuit,

a counting register constituted by a count-down register which can bepreset at the number N of periods intended to constitute the timestandard, and the operation of which is initiated by the arrival of theclock pulses,

a first detector for detecting the n" active clockpulse front at theoutput of the synchronizing circuit and comprising a first matchabledelay line,

a second detector for detecting the (N n)" active clock-pulse front,said detector being controlled by the counting register and comprising asecond matchable delay line,

two identical output amplifying circuits for collecting respectively anddirectly said n and (N n)"' active clock-pulse fronts which the firstand the second detectors have selected and allowed to pass in order toconvert them into utilizable signals.

In accordance with a further characteristic feature of the generatorwhich forms the subject of this invention, the first detector fordetecting the n" active clockpulse front is constituted by a memorycell, a delay line and an AND-gate, the first input or so-calledpermission input of said gate being coupled to the output of the delayline and the second input being coupled to the clock.

In accordance with another preferred characteristic feature of thisinvention, said counting register which can be preset at the number N isa count-down register and said second detector for detecting the (N n)"active clock-pulse front comprises:

a detector for detecting the zero of the counting register, constitutedby AND-gates which receive the indications of state of all the dividersconstituting the register,

a second memory cell mounted immediately after said zero detector,

a second delay line,

and a second AND-gate of which the first input or socalled permissioninput is coupled to the output of said second delay line and the secondinput of which is coupled to the clock.

In accordance with yet another preferred characteristic feature of thisinvention, said circuit for triggering and synchronizing with the frontsderived from the frequency standard oscillator comprises a firstsynchronizing circuit constituted by a memory cell which receives thetrigger pulse and is coupled to the permission input of an AND-gate ofwhich the second input is coupled to the standard oscillator, and asecond synchronizing circuit which is identical with the first andconnected to the output of the first by means of a delay line, theoutput of the AND-gate of said second circuit being intended to generatesaid clock pulses.

The value of the time-delay d -r of said line is chosen so as to ensurethat the time of transit of a pulse within the AND-gate of said firstsynchronizing circuit, said delay line and the memory cell of saidsecond synchronizing circuit is longer than the width of the pulse ofthe frequency standard oscillator, with the result that the pulse whichopens the AND-gate of said first synchronizing circuit cannot also passthrough the AND-gate of said second synchronizing circuit.

In accordance with another basic design feature of the time intervalgenerator which forms the subject of the invention, the n'" and (N n)"active clock-pulse fronts are transmitted respectively and directly tothe two identical output amplifying circuits through said two AND-gateswhich form part respectively of the first and second detectors.

The adjustable time-delays chosen, namely d-r, and d-r respectively ofthe first and second detectors, are such that the n" active clock-pulsefront should be the first to be detected by the first detector, that the(N n)" active clock-pulse front should be the first to be detected bythe second detector and that the permission for opening each gate of thefirst and of the second detector respectively should be given asufficient length of time beforehand with substantially the same phaselead with respect to the n" and to the (N n) active clock-pulse frontrespectively.

Finally, in accordance with the invention, each output amplifyingcircuit of the generator comprises a memory cell, a differentiatingcircuit, an amplifier proper, and a stage for injecting inverse currentinto a snap-off diode which is in turn under the control of a currenthaving a variable bias as a function of the temperature. Thislast-mentioned feature makes it possible to maintain at identical valuesthe respective transit times of the signal between the input and theoutput of each amplifying circuit.

As is apparent, one of the properties of this generator lies in the factthat the first detector must detect only the n" active clock-pulse frontand preferably the second. This is necessary by reason of the fact thatthe synchronization is not perfect, that the first pulse front emittedby the clock after a triggering order is always of slightly variableoccurrence and it is advisable not to consider the first period. (Forexample, in the case of a rectangular oscillation having a period Twhich is equal to ns, this random variation is of the order of 100 ps).Since the second detector is adjusted so as to detect the pulse front ofthe order (N n) and preferentially the front of the order (N 2), thedifference between the two detected fronts in fact remains equivalent toNT periods in accordance with the desired object.

Further characteristic features of this invention will in any casebecome apparent from the following description of one example ofapplication of the method and of the generator for obtaining standardtime intervals in accordance with the present invention. Thisdescription, which is given by way of indication without any intendedlimitation, will be given with reference to the accompanyingdiagrammatic FIGS. 1 to 5, wherein:

FIG. I is a general arrangement diagram which serves to illustrate theprinciple of operation of the generator in accordance with theinvention;

FIG. 2 shows a memory cell which is employed in the generator accordingto the invention, respectively in its state X (FIG. 2a) and in its stateY (FIG. 2b);

FIG. 3, which is split up into two parts 3a and 3b for the sake ofenhanced clarity, is a detailed diagram of the electronic circuitry ofthe generator of FIG. 1;

FIG. 4 is a detailed electronic diagram of one of the amplifiers of FIG.I;

FIG. 4a is a detailed electronic diagram of a portion of FIG. 4.

FIG. 5 is a diagram showing the time-variation of the different pulseswhich travel within the main circuits, respectively in the two detectorsD, and D and in the amplifiers A, and A of FIG. 1.

The general arrangement diagram which is given in FIG. 1 represents astandard time interval generator in accordance with the presentinvention. There are shown in this diagram a frequency standardoscillator OE, a trigger circuit DEC and a circuit M4) for synchronizingthis triggering order, a count-down register RD made up of five decadescalers in which the first scaler is split up into two sections, namelya scale-of-two divider and a scale-of-five divider. There is also shownin FIG. 1 the detector D, which is constituted respectively by a memorypoint 32, a delay line LR, and an AND- gate 4, the detector D which isconstituted respectively by a coincidence circuit 49, a memory point 62,a delay line LR and an AND-gate 5 as well as two amplifiers A, and A Theoperation of the system as thus described is as follows: the number N ofclock pulses with which it is desired to constitute the standard timeinterval is first indicated in the count-down register RD. When an orderfor initiating the production of the standard time interval reaches theline 1 (this order can be given either manually or in conjunction withan external and random phenomenon, or alternatively in a periodic formby means of relaxation oscillations), the trigger circuit DEC and thecircuit M for synchronizing this triggering order permits the passage inthe line 2 of the pulses emitted by the standard oscillator OE after thetriggering order has been given, thereby obtaining the clock H. Withinthe detector D,, the memory point 32 changes state at the time ofarrival of the front of the initial pulse of the clock H on the line 22,but the delay line LR, introduces in the step produced by said change ofstate a time-delay d'r,, with the result that said step is caused toarrive on the line 3a only after the end of the initial clock pulse. Atthis moment the sensitized gate 4 is ready to permit the transmission ofthe second pulse as soon as it arrives on the line 3b, said pulse beingdelivered by the clock H as a result of the triggering order. A step I,then passes into the amplifying circuit A, which delivers at S, a pulserepresenting the time of appearance of the second clock-pulse front.

As the clock pulses arrive on the line 2, so the countdown register RDbegins to count-down and is cleared at the N" pulse as established bythe zero detector 49; the memory point 62 then sends a step towards thedelay line LR This step is transmitted to the second AND-gate 5 by thedelay line LR only after a time delay dr The time-delay dr is socalculated that the preceding step reaches the AND-gate 5 only afterextinction of the clock pulse of the order (N I), thus conditioning saidgate 5 and then enabling this latter to permit the transmission of theclock pulse of the order (N 2) into the amplifying circuit A in the formof the step I Said amplifying circuit delivers at its output a pulse Scorresponding to the pulse front of the clock H of the order (N 2). Thestandard time interval produced by the generator is defined by the timewhich elapses between the two small-width pulses S, and S Beforeproceeding to a more complete description of the electronic diagram ofFIG. 3, there will now be described an electronic unit which isfrequently employed in this diagram of FIG. 3 and designated throughoutthis description as a memory cell. This circuit is a bistable device RS,that isto say a circuit having two stable states X and Y, the state Xbeing shown in FIG. 2a and the sate Y being shown in FIG. 2b. Thismemory cell of known type is made up of two identical logic circuits,namely a gate A and a gate B which are mounted as shown in the figure.The output of each gate is connected to the input of the other and thesecond input of the gate B is coupled to a zero reset circuit RAZ. Inthe figures, the voltages (zero or one) corresponding to the stablestates have been indicated in each case.

Reference will now be made to FIG. 3, in which the functional elementsalready represented in detail in FIG. 1 are again shown and surroundedby dashed-line rectangles. There can thus be seen (in FIG. 3a) the line1 on which the triggering order initiates operation of the triggercircuit DEC proper composed of a monovibrator 6 followed by adifferentiator 8 which delivers the trigger pulse. The synchronizingcircuit M proper which immediately follows is double; the first stage ismade up ofa memory cell 10 and a gate 14, the permission input of whichis coupled to said memory cell; the second stage is composed of a memorycell 12 and of a gate 16, the permission input of which is coupled tothe memory cell 12, the gate 14 and the gate 16 being connected to theclock H; a delay line 18 separates the two synchronization stages andcouples the gate 14 to the input of the memory cell 12. The line 2 inwhich the clock pulses travel from the output of the synchronizingcircuits Md) is connected at 22 (see FIG. 3b) to the input of thedetector D said line 2 is also connected at 24 through an inverter gate26 on the one hand to the input of the scale-of-two divider 28 and onthe other hand to the input 30 which is common to the gates 4 and 5. Thedetector D comprises the memory cell 32 whose output S is connectedthrough the delay line LR, and the line 3a to the permission input ofthe gate 4.

The count-down register RD is made up of the scaleof-two divider 28, thescale-of-five divider 34 and the four decade scalers 36, 38, 40 and 42.The scale-of-two divider 28 is made up in known manner of a memory cell44 and of two AND-gates 46 and 48.

The coincidence circuit 49 is made up of the complete assembly of sixAND-gates 50, 52, 54, 56, 58 and 60. The first five gates are coupledrespectively to the scale-of-five divider 34 and to the four decadescalers 36, 38, 40 and 42 and are mounted between them in series. AnAND-gate 60 receives both the signal delivered from the gate 44 of thedivider 28 and the matched output of the AND-gate 50. The output of thegate 60 leads to a memory cell 62. The output E of said memory cell isconnected through the delay line LR to one of the inputs of the gate 5.

The inputs of two memory cells 64 and 66 are driven from the output ofthe two AND-gates 4 and 5 and each form part of the amplifying circuitsA, and A respectively; the description of one of these latter will nowbe given with reference to FIG. 4.

There is shown in FIG. 4 a memory cell 64 followed by a differentiator65, an amplifier 68 proper and a current-injecting stage 70 formed by atransistor T which injects an inverse current I into a snap-off diode72; an element 74 controls the operation of this diode 72 by producing adirect-biascurrent i, and by adjusting the value of this current independence on the ambient temperature in such manner as to ensure thatthe pulse transit time remains constant and identical in both amplifyingcircuits. Finally, a diode 76 is placed in the circuit in the forwarddirection towards the output S.

The element 74 comprises one or a number of diodes representing thetemperature variation and connected to the input of an operationalamplifier followed by an emitter-follower amplifier; the currentdelivered by this amplifier assembly varies as a function of the voltagedeveloped across the terminals of said diode; this compensates for thevariation in life-time of the carriers in the snap-off diode, with theresult that the overlap time of the snap-off diode remains constant as afunction of the temperature. The elements are identical in bothchannels. As seen in FIG. 4a, element 74 includes resistance r r r and rand a transistor T of the NPN type whose base is connected to the outputof an amplifier A. The emitter of transistor T is connected throughresistance r,,- to a source of potential -V,, and to the inverse entryof amplifier A through resistance r The collector of the transistor isconnected to transistor 70. The diodes D compensate for temperatureeffects on the snap-off diode 72. Voltages V and V regulate the value ofthe current i and the gain of amplifier A (resistances R and R fixes therelation between the temperature and the current The amplifying deviceof FIG. 4 makes it possible to obtain a step which has an amplitude of20 V and a rise time of approximately 300 ps while being in welldefinedand stable phase relation with an active front of the clock; its outputcan be connected to a low impedance such as 50 ohms, for example.

The general operation of the system will now be described below withreference in particular to FIGS. 3a, 3b and 5. For the sake of greaterclarity, the binary transitions from 1 to 0 or from O to l which takeplace at the different stages of this operation have been represented insitu by means of arrows.

At the time of arrival of a triggering order on the line 1 (FIG. 3a),the monovibrator 6 and the differentiator 8 emit a triggering pulsewhich causes a change of state of the memory cell 10 of the first stageof the synchronizing circuit Md); the gate 14 then permits transmissionof the pulse which is derived from the standard oscillator OE andappears first; this latter is retarded by the delay line 18; theretarded pulse causes a reversal of state of the memory cell 12 of thesecond stage of the synchronizing circuit, thereby permitting thetransmission through the gate 16 of the pulse derived from the followingstandard oscillator; synchronization is thus carried out and haspermitted transmission to the line 2 of the clock pulses H asrepresented at D in FIG. 5. The design function of the delay line 18 isto prevent the pulse which has been transmitted by the gate 14 and haschanged the state of the memory point 12 from again passing through thegate 16 by virtue of the speed of the circuits employed and of the widthof the pulses of the standard oscillator OE. The assembly consisting ofgate 14, delay line 18, memory point 12 makes it possible to ensureopening of the gate 16 at a correct instant, with the result that thefirst clock pulse which appears on the line 2 is strictly in phase withthe pulse derived from the standard oscillator OE and that the initialclock period is strictly equal to that of the standard oscillator OE.

Before switching-on the apparatus, all the memory cells had been resetto zero by the circuits provided for this purpose and designated inFIGS. 3a and 3b by the letters RAZ and were consequently in the state Xcorresponding to FIG. 2a. It will be noted that the reset pulse which isapplied to the memory points 10 and 12 prevents the pulses derived fromthe standard oscillator OE from arriving on the line 2. The arrival ofthe first pulse front of the clock H on the line 2 at the output of thesynchronizing circuit Mqb causes a change of state of the memory cell 32and there is found at the output the step which is indicated in FIG. 5and displaced by a time interval 1', corresponding to overstepping ofthis circuit 32 with respect to the leading edge of the initial pulse ofthe clock H. The memory cell 32 of the detector D1 has changed to stateland the change-over to the zero state at the output S permits with atime-delay a 'r introduced by the delay line LR the opening of the gate4 by the following second pulse front of the clock H. The displacementd'r of the state of the line g with respect to the state S of the sameline 81 is shown at D1 in the diagram of FIG. 5 and is chosen so as tobe located after the initial pulse of the clock and nevertheless at asufficient distance from the second to enable the circuit to prepare forthe reception of this second pulse. Said second pulse gives rise at theoutput S, of the memory cell 64 to a pulse I which is delayed by 1- withrespect to the second pulse E, this wave being in turn delayed withrespect to H by the time interval T2. In the example described, theperiod D of the clock H is 10 ns; this clock is a quartz oscillatorhaving a frequency of 5 Mc/s followed by a scale-of-twenty multiplier inorder to attain a frequency of 100 Mc/s, the last stage of themultiplier being a quartz filter which operates at I00 Mc/s. It isapparent from the diagram of FIG. 5 that the time-delay of a -r whichhas been chosen is of the order of 3 ns.

The clock pulses on the line 24 arrive at the inverter gate 26 whichdelivers at its output, with a time-delay 7 resulting from thetransmission through said gate 26, a signalfi which is shown in FIG. 5at D and D At this moment, the count-down register RD comes intooperation; as the different decade scalers are cleared, so the AND-gates58, 56, 54, 52 come into operation until the gate 50 which is in turnsensitized causes the initial state on the line 78 constituting one ofthe inputs of the AND-gate 60 to change from one to zero. This change ofstate takes place after the point of the order (N l) with a time-delay1- which is substantially equal to 8 ns corresponding to the propagationtime within the scaleof-two divider 28, the first flip-flop of thescale-of-five divider 34 and the gate 50. When the scale-of-two divider28 also arrives at zero and when the second input of the gate 60 changesstate from one to zero on the line 80, this gate in turn transmits asignal in the form of a change of state from zero to one within thememory cell 62. This change of state takes place at N'" pulse with, asindicated in FIG. 5 at D reference 80, a timedelay 1-,, of approximately8 ns with respect to the front of the N"' pulse I-I resulting from thepassage of the pulses within the scale-of-two divider 28.

There appears at the output of the memory cell 62 the step S? which isdelayed by 1 with respect to the signal Q1 by reason of the time oftransit within the AND-gate 60 and the memory cell 62; there thenappears at the input of the gate 5 the step S as deducted from thepreceding by the time-delay d'r which is introduced by the line LR Theamplitude (172 of this timedelay is chosen in such manner that the stepC takes place after the disappearance of the pulse of the order (N l) ofthe clock H. At the output 8, of the memory cell 62, there is thenobtained the pulse 1 (at A of FIG. 5) which occurs only after a timeinterval which is displaced by -r with respect to the leading edge ofthe pulse of the order (N 2) of the clock H by reason of the transittime within the AND-gate 5 which is identical with the AND-gate 4 andwithin the memory cell 66 which is identical with the memory cell 64.

Finally, the third portion (A and A of the diagram of FIG. 5 shows howthe final pulses S1 and S2, the spacing of which defines the timestandard produced, are obtained through amplifiers A1 and A2 inaccordance with the diagram of FIG. 4 from pulses l1 and I2 which aredelivered respectively by the memory cells 64 and 66.

I claim:

1. A generator for producing a standard time interval 1' NT delimited bytwo fronts separated by N periods of a periodic and preferablysubstantially rectangular oscillation having a period T and generated bya frequency standard oscillator, wherein said generator comprises incombination:

a circuit for triggering and synchronizing with the fronts derived fromthe frequency standard oscillator, there being transmitted by saidcircuit only those pulses of said frequency standard oscillator whichcome after an order given by said trigger circuit as clock pulses,

a counting register constituted by a count-down register which can bepreset at the number N of periods to constitute the time standard, andthe operation of which is initiated by the arrival of the clock pulses,

a first detector for detecting the n'" active clockpulse front at theoutput of the synchronizing circuit,

a second detector for detecting the (N n)" active clock-pulse front,said detector being controlled by the counting register,

two identical output amplifying circuits for collecting respectively anddirectly said 11 and (N n)" active clock-pulse fronts which the firstand second detectors have selected and allowed to pass in order toconvert them into utilizable signals.

2. A generator according to claim 1, wherein the first detector fordetecting the n active clock-pulse front is constituted by a memorycell, a delay line and an AND-gate, the first permission input of saidgate being coupled to the output of said delay line and the second inputbeing coupled to the clock.

3. A generator according to claim 1, wherein said counting registerwhich can be preset at the number N is a count-down register and saidsecond detector for detecting the (N n)"' active clock-pulse frontcomprises:

a detector for detecting the zero of the counting register constitutedby AND-gates which receive the indications of state of all the dividersconstituting the register,

a second memory cell mounted immediately after said zero detector,

a second delay line,

and a second AND-gate of which the first permission input is coupled tothe output of said second delay line and the second input of which iscoupled to the clock.

4. A generator according to claim 1, wherein said circuit for triggeringand synchronizing with the fronts derived from the frequency standardoscillator comprises a first synchronizing circuit constituted by amemory cell which receives the trigger pulse and is coupled to thepermission input of an AND-gate of which the second input is coupled tothe standard oscillator, and a second synchronizing circuit which isidentical with the first and connected to the output of the first bymeans of a delay line, the output of the AND-gate of said second circuitbeing intended to generate said clock pulses.

5. A generator according to claim 2, wherein the adjustable time-delaysd'r and 111- of the delay lines of the first and of the second detectorrespectively are chosen in such manner that the n" or the (N n)" activeclock-pulse front is the first to be detected by the correspondingdetector and that the permission for opening each gate of the first andof the second detector respectively is given a sufficient length of timebeforehand with substantially the same phase lead with respect to the n"or the (N n)"' active clock-pulse front respectively.

6. A generator according to claim 1, wherein each output amplifyingcircuit comprises a memory cell, a differentiating circuit, an amplifierproper, and a stage for injecting inverse current into a snap-off diode.

7. A generator according to claim 6, wherein the snap-off diode of eachoutput amplifying circuit is under the control of an element forproducing a current having a variable bias as a function of thetemperature in order to maintain at identical values the times oftransit of the signal between the input and the output of each of thetwo amplifying circuits.

8. A generator according to claim 7, wherein said element comprises atleast one diode, an operational amplifier whose input is connected tothe terminals of said diode and an emitter-follower amplifier.

1. A generator for producing a standard time interval Tau NT delimitedby two fronts separated by N periods of a periodic and preferablysubstantially rectangular oscillation having a period T and generated bya frequency standard oscillator, wherein said generator comprises incombination: a circuit for triggering and synchronizing with the frontsderived from the frequency standard oscillator, there being transmittedby said circuit only those pulses of said frequency standard oscillatorwhich come after an order given by said trigger circuit as clock pulses,a counting register constituted by a count-down register which can bepreset at the number N of periods to constitute the time standard, andthe operation of which is initiated by the arrival of the clock pulses,a first detector for detecting the nth active clock-pulse front at theoutput of the synchronizing circuit, a second detector for detecting the(N + n)th active clock-pulse front, said detector being controlled bythe counting register, two identical output amplifying circuits forcollecting respectively and directly said nth and (N + n)th activeclockpulse fronts which the first and second detectors have selected andallowed to pass in order to convert them into utilizable signals.
 2. Agenerator according to claim 1, wherein the first detector for detectingthe nth active clock-pulse front is constituted by a memory cell, adelay line and an AND-gate, the first permission input of said gatebeing coupled to the output of said delay line and the second inputbeing coupled to the clock.
 3. A generator according to claim 1, whereinsaid counting register which can be preset at the number N is acount-down register and said second detector for detecting the (N + n)thactive clock-pulse front comprises: a detector for detecting the zero ofthe counting register constituted by AND-gates which receive theindications of state of all the dividers constituting the register, asecond memory cell mounted immediately after said zero detector, asecond delay line, and a second AND-gate of which the first permissioninput is coupled to the output of said second delay line and the secondinput of which is coupled to the clock.
 4. A generator according toclaim 1, wherein said circuit for triggering and synchronizing with thefronts derived from the frequency standard oscillator comprises a firstsynchronizing circuit constituted by a memory cell which receives thetrigger pulse and is coupled to the permission input of an AND-gate ofwhich the second input is coupled to the standard oscillator, and asecond synchronizing circuit which is identical with the first andconnected to the output of the first by means of a delay line, theoutput of the AND-gate of said second circuit being intended to generatesaid clock pulses.
 5. A generator according to claim 2, wherein theadjustable time-delays d Tau 1 and d Tau 2 of the delay lines of thefirst and of the second detector respectively are chosen in such mannerthat the nth or the (N + n)th active clock-pulse front is the first tobe detected by the corresponding detector and that the permission foropening each gate of the first and of the second detector respectivelyis given a sufficient length of time beforehand with substantially thesame phase lead with respect to the nth or the (N + n)th activeclock-pulse front respectively.
 6. A generator according to claim 1,wherein each output amplifying circuit comprises a memory cell, adifferentiating circuit, an amplifier proper, and a stage for injectinginverse currenT into a snap-off diode.
 7. A generator according to claim6, wherein the snap-off diode of each output amplifying circuit is underthe control of an element for producing a current having a variable biasas a function of the temperature in order to maintain at identicalvalues the times of transit of the signal between the input and theoutput of each of the two amplifying circuits.
 8. A generator accordingto claim 7, wherein said element comprises at least one diode, anoperational amplifier whose input is connected to the terminals of saiddiode and an emitter-follower amplifier.